A memory device is used by electronic devices to store data. Data stored in a memory device are represented by binary digit (bit) patterns formed from single bits, where each single bit has typically two possible values: a logic 0 and a logic 1. The memory device stores the bit patterns in memory elements that have different states corresponding to different possible values. For example, a two-state memory element having a first state corresponding to a logic 0 and a second state corresponding to a logic 1 can store a single bit. Some memory devices are capable of storing more than two states, e.g., a four-state memory element having a first state corresponding to a logic 00, a second state corresponding to a logic 01, a third state corresponding to a logic 10, and a fourth state corresponding to a logic 11 can store two bits. In general, an n-state memory element can store log2 n bits, where log2 n refers to the binary logarithm of n.
The marketplace demand for low cost memory devices at lower costs with data storage capacities has spurred the creation of memory devices with increased memory densities. The traditional way of measuring memory density is the number of bits stored per square millimeter of layout area consumed (bits/mm2). Therefore, the memory density of a memory device can be increased by: reducing the feature sizes of memory elements to consume less layout area, and increasing the number of bits memory elements can store. Vertically stacking memory layers to form a three-dimensional memory structure does not substantially increase the size of the memory device or layout area because the vertical dimension remains relatively small. Thus, bits/mm2 remains a valid way of measuring memory density. Two memory layers doubles the memory density resulting in doubling the memory functionality in the approximately same layout area.
Resistive change memory is a technology well suited to meet the marketplace demand for low cost memory devices with higher data storage capacities. A resistive change memory device has resistive change memory elements that are scalable to very high densities, incur very low fabrication costs, store nonvolatile memory states, and consume very little power. Typically, the resistive change memory device stores data by adjusting the state of resistive change memory elements through adjusting the state of a state-adjustable material between a number of nonvolatile resistive states in response to applied stimuli. For example, a two-state resistive change memory element can be configured to switch between a first resistive state (e.g., a high resistive state) that corresponds to a logic 0 and a second resistive state (e.g., a low resistive state) that corresponds to a logic 1. Using these two resistive states, the two-state resistive change memory element can store a single bit. Similarly, a four-state resistive change memory element can be configured to switch between a first resistive state (e.g., a very high resistive state) that corresponds to a logic 00, a second resistive state (e.g., a moderately high resistive state) that corresponds to a logic 01, a third resistive state (e.g., a moderately low resistive state) that corresponds to a logic 10, and a fourth resistive state (e.g., a very low resistive state) that corresponds to a logic 11. Using these four resistive states, the four-state resistive change memory element can store two bits.
The electrically programmable read-only memory (EPROM) device disclosed by Roesner in U.S. Pat. No. 4,442,507 is a type of resistive change memory having two-state resistive change memory elements with the two-state resistive change memory elements having resistive materials in a series connection with Schottky diodes. The EPROM device stores data in the two-state resistive change memory elements by adjusting a resistance state of the resistive materials. Prior art FIG. 1 generally corresponds to FIG. 11 of U.S. Pat. No. 4,442,507 and prior art FIG. 1 illustrates a two-state resistive change memory element 10 formed by a resistive material 50 in a series connection with a Schottky diode 52. The resistive material 50 consists essentially of a single element semiconductor selected from the group of Si, Ge, C, and α-Sn, and is deposited as a layer of 2,000 Å thickness. The resistive material 50 has a high resistance state on the order of 107 ohms before an electrical stimulus is applied and a low resistance state on the order of 102 ohms after the electrical stimulus is applied.
During a write operation the EPROM device adjusts the resistance state of the two-state resistive change memory element 10 by supplying an electrical stimulus in the form of a programming voltage above a desired threshold voltage to the two-state resistive change memory element 10. The application of the programming voltage causes the resistive material 50 to irreversibly switch from the high resistance state to the low resistance state. During a read operation the EPROM device senses the resistance state of the two-state resistive change memory element 10 by supplying a preselected voltage and current to the two-state resistive change memory element 10. The preselected voltage is limited to a preselected value below the desired threshold voltage for switching the resistance state of the resistive material 50 and the resulting current are limited to below a preselected value. The high resistance state and the low resistance state of the resistive material 50 produce different voltages across and different currents flowing through the two-state resistive change memory element 10 in response to the EPROM device supplying the preselected voltage and current. Roesner provides the exemplary voltage across and current flowing through the two-state resistive change memory element 10 with the resistive material 50 in the high resistance state of 5 V and 0.2 μA respectively, and the exemplary voltage across and the current flowing through the two-state resistive change memory element 10 with the resistive material 50 in the low resistance state of 0.25 V and 50 μA respectively. The different voltages and currents sensed by the EPROM device are interpreted as data stored in the two-state resistive change memory element 10. Additionally, the resistive change memory element 10 is non-volatile because power is not required to maintain the different resistance states of the resistive material 50, and thus, the data is retained in the two-state resistive change memory element 10 when power is removed.
In operation, the EPROM device disclosed by Roesner is formed with a Schottky diode and a nonvolatile programmable resistor in a relatively high resistance initial state as fabricated. Decode circuits and Schottky diodes in each cell may be used to selectively cause nonvolatile programmable resistor values to transition to a relatively low resistance permanent state. That is, the EPROM-EROM is a one-time-programmable (OTP) memory. After the programming operation is completed, the EPROM device operates as a read-only memory.
The two-state resistive change memory element 10 illustrated in prior art FIG. 1 is fabricated on an insulating layer 12 of SiO2 that is deposited over a semiconductor substrate 11 containing circuitry for the EPROM device. The insulating layer 12 is 7,000 Å-10,000 Å thick to smooth out surface 12a and also to minimize any capacitances between the two-state resistive change memory element 10 and the underlying circuitry for the EPROM device. The two-state resistive change memory element 10 is constructed from a semiconductor lead 14, an insulator 16, the Schottky diode 52, the resistive material 50, and a metal lead 20.
The semiconductor lead 14 has a polycrystalline layer of N+ semiconductor material deposited on the surface 12a of the insulating layer 12 and a polycrystalline layer of N− semiconductor material deposited on the polycrystalline layer of N+ semiconductor material. The polycrystalline layer of N+ semiconductor material and the polycrystalline layer of N− semiconductor material are fabricated by depositing either silicon or germanium and then doping the silicon or the germanium in-situ. The polycrystalline layer of N+ semiconductor material has a dopant atom concentration of at least 1020 atoms/cm3 and the polycrystalline layer of N− semiconductor material has a dopant atom concentration of 1014-1017 atoms/cm3 with arsenic, phosphorous, and antimony being suitable dopant impurity atoms for both polycrystalline layers. The insulator 16 is then formed by depositing a layer of SiO2 over the surface 12a and the semiconductor lead 14 with subsequent masking and etching of the insulator 16 to form a contact hole over the semiconductor lead 14. Thereafter, the semiconductor lead 14 and the insulator 16 are annealed at 900° C. to increase the crystalline grain size of both polycrystalline layers in semiconductor lead 14 and to move the dopant atoms from interstitial to substitutional positions in the lattice network of both polycrystalline layers in the semiconductor lead 14.
The Schottky diode 52 has a cathode formed by the polycrystalline layer of N− semiconductor material of the semiconductor lead 14 and an anode formed by a platinum compound (e.g. platinum silicide) 18. The Schottky diode 52 is fabricated by depositing a layer of platinum on the exposed portion of the polycrystalline layer of N− semiconductor material and heating the layer of platinum to 450° C. to form the platinum compound (e.g. platinum silicide) 18 with the polycrystalline layer of N− semiconductor material. The resistive material 50 is then deposited on the platinum compound with special care taken throughout the fabrication process to prevent the resistive material 50 from being exposed to temperatures greater than 600° C. This temperature constraint is imposed on the fabrication process to ensure that the crystalline grain size of the resistive material 50 is substantially smaller than the crystalline grain size of the polycrystalline layer of N− semiconductor material of the semiconductor lead 14 and also to ensure that any dopant atoms in the resistive material 50 are interstitial in the lattice instead of substitutional. Additionally, the amount of current required for resistive material 50 to switch resistance states is dependent on the maximum temperature that the resistive material 50 is exposed to with the amount of current required for the resistive material 50 to switch resistance states increasing in a highly nonlinear manner as the maximum temperature increases. Roesner provides the example of when the resistive material 50 is processed at a maximum temperature of 600° C. the resistive material 50 might require only 10 μA to switch resistive states and when the resistive material 50 is processed at a maximum temperature of 750° C. the resistive material 50 might require several milliamps to switch resistance states.
The metal lead 20 has a bottom layer 22 formed by a barrier metal and a top layer 24 formed by a conductive metal. The barrier metal prevents the conductive metal from migrating into the resistive material 50. The metal lead 20 is fabricated by depositing the bottom layer 22 of titanium tungsten on the resistive material 50 and the top layer 24 of aluminum on the bottom layer of titanium tungsten.